As advanced complementary metal-oxide-semiconductor (CMOS) technology continues to scale and move into the deep-sub-micron geometry dimensions, the optimization of channel profile and source/drain regions has become complex. A desire to provide high saturation currents and low off-currents calls for a low subthreshold swing and high channel mobility, while suppressing short channel effects calls for high channel doping. Conventional channel doping profiles are insufficient to provide for low voltage threshold and acceptable short channel behavior as the scale of advanced CMOS technology decreases.
Super steep retrograde wells (SSRWs) have been developed, in which a dopant concentration in areas of the channel region further from a gate dielectric of the transistor is higher than dopant concentration in areas that are adjacent to the gate dielectric. The SSRWs effectively suppress short channel effects while maintaining a low subthreshold swing and a low voltage threshold. However, a concentration gradient of dopants in the SSRWs is typically limited by diffusion characteristics of the dopant in the channel region. One difficulty associated with forming the SSRWs is due to diffusion of the dopant in the SSRW through the channel region toward, and possibly into, the gate dielectric and gate electrode. One technique that has been developed to address diffusion of the dopant in the SSRW through the channel region is formation of a doped layer within a semiconductor substrate with a carbon-doped silicon layer disposed in the channel region between the doped layer and the gate dielectric. The carbon in the carbon-doped silicon suppresses interstitial diffusion, such as diffusion of dopant from the doped layer through the carbon-doped silicon layer, thereby effectively blocking diffusion of common dopants (such as boron in p-well configurations) in the channel region toward the gate dielectric. However, the capacity of the carbon-doped silicon layer to suppress interstitial diffusion can become depleted in the carbon-doped silicon layer during source/drain region formation, which generally introduces interstitials into the channel region from the source region and the drain region and thereby degrades the effectiveness of the carbon-doped silicon layer to suppress interstitial diffusion from the SSRW toward the gate dielectric.
Accordingly, it is desirable to provide semiconductor devices and methods of forming semiconductor devices including SSRW configurations in a channel region between a source region and a drain region, with enhanced suppression of interstitial dopant diffusion in the channel region toward a gate dielectric. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description of the invention and the appended claims, taken in conjunction with the accompanying drawings and this background of the invention.